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FEDL1200V-03
FEDL1200V-03 This version: Sep. 2000 MSC1200-01/1200V-01 Previous version: Nov. 1997
Semiconductor MSC1200-01/1200V-01
Semiconductor
30-Bit Duplex Controller/Driver with Digital/Analog Dimming and Keyscan Functions
GENERAL DESCRIPTION
The MSC1200-01/1200V-01 is a Bi-CMOS display driver for 1/2-duty vacuum fluorescent display tube. This device consists of a 64-bit shift register, latches, an analog dimming circuit, a digital dimming circuit, a keyscan circuit, and drivers. The interface with a microcomputer can be done only with four signal lines (CS, DATA I/O, CLOCK, and INT). Also, the DATA I/O and CLOCK signal lines can be shared with other peripherals by using the chip select function.
FEATURES
* Power supply voltage : 8V to 18V (built-in 5V regulator for logic) * Operating temperature range : -40C to +85C * 30-segment driver outputs (IOH = -6mA at VOH = VDD - 0.8V) * Built-in analog dimming circuit (PWM: 12.5% Max at 6-bit resolution) * Built-in digital dimming circuit (11-bit resolution) * Built-in 5 x 6 keyscan circuit * Built-in RC oscillation circuit (external R and C) * Built-in power-on-reset circuit. * The product name differs depending on the bonding option pin selected: PWM OUT/BLANK IN : MSC1200-01 DATA OUT : MSC1200V-01 * Package : 56-pin plastic QFP (QFP56-P-910-0.65-2K) (Product name: MSC1200-01GS-2K/MSC1200V-01GS-2K)
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FEDL1200V-03 Semiconductor MSC1200-01/1200V-01
BLOCK DIAGRAM
SEG1 5V VDD GND 5V Regulator &POR POR 30 Segment Drivers Grid Driver SEG30 GRID1 GRID2
PLA (32 32 Matrix)
TEST1
Multiplexer
S1 S2 S3 S4 S5 S6 S7 S8 S9 SA
Bit Latch
Mode Selector
D CK S1, S6, S7, S8 OSC0 OSC1 R/C OSC
64-Bit Shift Register R
M3 M2 M1 M0
DATA OUT (Optional)
Timing Generator R
VPARK VDIM
Analog Dimming R Selector Digital Dimming R S4 S9 SA R S2, S7, S3, S8 INT PWM OUT/ BLANK IN (Optional)
CS DATAI/O CLOCK
Control Circuit S5, S6, S9
5 6 Keyscan Circuit
0 1 2 34 5 COLUMN
0 1 2 34 ROW
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FEDL1200V-03 Semiconductor MSC1200-01/1200V-01
INPUT AND OUTPUT CONFIGURATION
* Schematic Diagrams of Logic Portion Input Circuit
VDD (5V Reg.)
INPUT
GND
GND
* Schematic Diagrams of Logic Portion Input * Schematic Diagrams of Logic Portion Input/ Circuit 2 Output Circuit
VDD TEST1 COLn DATAI/O (5V Reg.) (5V Reg.) VDD (5V Reg.)
GND
GND
GND
GND
GND
GND
* Schematic Diagrams of Logic Portion Output * Schematic Diagrams of Driver Output Circuit Circuit
(5V Reg.) (5V Reg.) VDD VDD
OUTPUT
OUTPUT
GND
GND
GND
GND
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FEDL1200V-03 Semiconductor MSC1200-01/1200V-01
PIN CONFIGURATION (TOP VIEW)
54 SEG30 53 SEG29 52 SEG28 51 SEG27 50 SEG26 48 SEG25 47 SEG24 46 SEG23 45 SEG22 44 SEG21 SEG4 27 43 SEG20 56 GRID2 55 GRID1 49 GND
VDD 1 VPARK 2 VDIM 3 CS 4 CLOCK 5 DATA I/O 6 INT 7 TEST1 8 *1 9 COLUMN0 10 COLUMN1 11 COLUMN2 12 COLUMN3 13 COLUMN4 14
COLUMN5 15 ROW0 16 ROW1 17 ROW2 18 ROW3 19 ROW4 20 GND 21 OSC0 22 OSC1 23 SEG1 24 SEG2 25 SEG3 26 SEG5 28
42 SEG19 41 SEG18 40 SEG17 39 SEG16 38 SEG15 37 SEG14 36 SEG13 35 SEG12 34 SEG11 33 SEG10 32 SEG9 31 SEG8 30 SEG7 29 SEG6
56-Pin Plastic QFP
*1 Bonding option pin (DATA OUT or PWM OUT/BLANK IN)
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FEDL1200V-03 Semiconductor MSC1200-01/1200V-01
PIN DESCRIPTIONS
Pin 1 Symbol VDD VPARK Type -- Power Supply Day/night switching pin. When the high level is input, the IC enters the night mode and the value determined by the analog or digital dimming circuit is used as the output duty. When the low level is input, the IC enters the day mode and the output duty is about 100%. Analog voltage input for determining the analog dimming value. When the analog dimming circuit is used, the output duty is determined by the analog voltage to be input to this pin. When only the digital dimming circuit is used, pull down this pin to GND. Chip select input. Only when the high level is input to this pin, interfacing with a microcomputer is available through "CLOCK" and "DATA I/O" pins. Therefore, 2 signal lines of "CLOCK" and "DATA I/O" can be shared with other peripherals. Serial clock input. Data is input-output through "DATA I/O" pin at the rising edge of the serial clock. Serial data input-output. This pin enters output mode only when the keyscan mode is selected. It enters input mode when other mode is selected. Interrupt signal output to microcomputer. When any key is pressed or released, key scanning is started. After the completion of the one cycle, this pin goes to the high level and keeps the high level until keyscan stop mode is selected. Test signal input. As this pin has a built-in pull-up resistor, it must be left open or pulled up in the normal operation mode. When the low level is input to this pin, SEG1-30 go to the high level, and GRID1 and GRID2 go to the low level. (All segments go on.) Serial data output. Selecting this pin specifies the MSC1200V-01. The data from DATA I/O is shifted out on the rising edge of the shift clock with a delay of 64 bits in the shift register. This pin can be used for connecting the IC with a LED driver in series. When the VPARK pin is at the high level, the pulse with the duty ratio determined by the analog or digital dimming circuit is output through this pin. When this pin is at the low level, the pulse with the duty ratio determined by external circuit is input to this pin. This pin has an internal active pull-up resistor, which becomes active only when the VPARK pin is at the low level. When the VPARK pin is at the low level, this pin receives blanking signal from external circuits, so that output duty cycle can be controlled. Selecting this pin specifies the MSC1200-01. Description
2
I
3
VDIM
I
4
CS
I
5 6
CLOCK DATA I/O
I I/O
7
INT
O
8
TEST1
I
9
DATA OUT (Option)
O
9
PWM OUT/ BLANK IN (Option)
I/O
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FEDL1200V-03 Semiconductor MSC1200-01/1200V-01
Pin 10-15
Symbol COLUMN 0-5
Type I
Description Return inputs from key matrix switch. A pull-up resistor is internally connected to each of these pins so that they are at the high level except when the low level is input by depression of a key. These pins are "L" active. Key switch scanning outputs. Normally the low level is output through these pins. When any key is depressed or released, keyscanning is started and is continued until keyscan stop mode is selected. When the keyscan stop mode is selected and then keyscanning is stopped, all outputs of ROW0-4 go back to the low level. Ground Connecting pins for RC oscillation circuit. Connect a resistor between OSC1 and OSC0, and a capacitor between OSC0 and ground. Segment signal output. Signals for driving VF display tube are output through these pins. Grid signal output. Signals for driving VF display tube are output through these pins. Signals inverted with respect to grid signals are output. Normally, these pins are connected to the external grid driver (PNP transistor etc.) inputs.
16-20
ROW0-4
O
21, 49 22, 23 24-48, 50-54 55, 56
GND OSC0 OSC1 SEG1-30
-- I/O O
GRID1,2
O
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FEDL1200V-03 Semiconductor MSC1200-01/1200V-01
ABSOLUTE MAXIMUM RATINGS
Parameter Supply Voltage Input Voltage (1) Input Voltage (2) Storage Temperature Power Dissipation Symbol VDD VIN1 VIN2 TSTG PD Condition -- All inputs except VPARK VPARK -- Ta = 85C Rating -0.3 to +20 -0.3 to +6 -0.3 to VDD +0.3 -65 to +150 400 Unit V V V C mW
RECOMMENDED OPERATING CONDITIONS
Parameter Supply Voltage High Level Input Voltage (1) High Level Input Voltage (2) High Level Input Voltage (3) Low Level Input Voltage (1) Low Level Input Voltage (2) Clock Frequency OSC Frequency Frame Frequency Operating Temperature Symbol VDD VIH1 VIH2 VIH3 VIL1 VIL2 fC fOSC fFR Top Condition -- All inputs except VPARK & OSC0 VPARK OSC0 All inputs except OSC0 OSC0 -- R = 4.7kW, C=10pF fOSC=3MHz -- Min. 8 3.8 3.8 4.5 0 0 -- -- -- -40 Typ. -- -- -- -- -- -- -- 3.3 201 -- Max. 18 5.5 VDD 5.5 0.8 0.5 250 -- -- +85 Unit V V V V V V kHz MHz Hz C
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FEDL1200V-03 Semiconductor MSC1200-01/1200V-01
ELECTRICAL CHARACTERISTICS
DC Characteristics
(Ta = -40 to +85C, VDD = 8 to 18V) Parameter High Level Input Voltage (1) *1 High Level Input Voltage (2) *9 High Level Input Voltage (3) *2 Low Level Input Voltage (1) *10 Low Level Input Voltage (2) *2 High Level Input Current (1) *3 High Level Input Current (2) *4 High Level Input Current (3) *5 Low Level Input Current (1) *3 Low Level Input Current (2) *4 Low Level Input Current (3) *5 Input Leakage Current *6 Symbol VIH1 VIH2 VIH3 VIL1 VIL2 IIH1 IIH2 IIH3 IIL1 IIL2 IIL3 IIL VOH1 VOH2-1 VOH2-2 VOL1-1 Low Level Output Voltage (1) *7 Low Level Output Voltage (2) *8 Power Supply Current VOL1-2 VOL1-3 VOL2 IDD Condition -- -- -- -- -- VIH1 = 5.0V VIH2 = 5.0V VIH3 = 5.0V VIL1 = 0V VIL2 = 0V VIL3 = 0V VI = 0 to 5.5V VDD = 9.5V, IOH1 = -6mA VDD = 9.5V, IOH2 = -200mA VDD = 9.5V, Output Open VDD = 9.5V, IOL1-1 = 500mA VDD = 9.5V, IOL1-2 = 200mA VDD = 9.5V, IOL1-3 = 2mA VDD = 9.5V, IOL2 = 200mA fOSC = 3.3MHz, No load Min. 3.8 3.8 4.5 0 0 -5 -30 -80 -5 -160 -0.6 -10 VDD -0.8 4 4.5 -- -- -- -- -- Max. 5.5 VDD 5.5 0.8 0.5 5 30 80 -5 -15 0.1 10 -- 6 6 2 1 0.3 0.8 20 Unit V V V V V mA mA mA mA mA mA mA V V V V V V V mA
High Level Output Voltage (1) *7 High Level Output Voltage (2) *8
Applicable to all input pins (except VPARK and OSC0 pins) Applicable to OSC0 pin Applicable to CLOCK, DATA I/O, CS, and VPARK pins Applicable to COLUMN0 to COLUMN5 and PWM OUT/BLANK IN pins Applicable to TEST1 pin Applicable to VDIM pin Applicable to SEG1 to SEG30, GRID1, and GRID2 pins Applicable to ROW0 to ROW4, DATA I/O, PWMOUT/BLANK IN, DATAOUT, and INT pins. *9 Applicable to VPARK pin *10 Applicable to all input pins (except OSC0)
*1 *2 *3 *4 *5 *6 *7 *8
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FEDL1200V-03 Semiconductor AC Characteristics
(Ta = -40 to +85C, VDD = 8 to 18V) Parameter Oscillation Frequency Input Frequency to OSC0 from Outside Frame Frequency PWM OUT Frequency Clock Frequency Clock Pulse Width Data Setup Time Data Hold Time CS Pulse Width CS Off Time CS Setup Time CS - Clock Time CS Hold Time Clock - CS Time Data Output Delay Clock - Data output Time SEG & GRID Output Delay from CS Slew Rate (All Drivers) CS Time at Power-on Hold Time at Power-off Rise Time at Power-on Symbol fOSC fOSCI fFR fPWM fC tCW tDS tDH tCSW tCSL tCSH tCSH tPD tODS tR tPCS tPOF tPRZ Condition R = 4.7kW1%, C = 10pF5% External input only -- -- -- -- -- -- -- -- -- -- -- CI = 100pF CI = 100pF, t = 20% to 80% or 80% to 20% of VDD -- When mounted on the unit VDD=0.0V When mounted on the unit Min. 2 2.4 122 244 -- 1.3 1 200 68 30 2 2 -- -- -- 300 5 -- Max. 4.66 3.7 284 568 250 -- -- -- -- -- -- -- 1 8 5 -- -- 100 Unit MHz MHz Hz Hz kHz ms ms ns ms ms ms ms ms ms ms ms ms ms
MSC1200-01/1200V-01
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FEDL1200V-03 Semiconductor MSC1200-01/1200V-01
Dimming Characteristics * DC characteristics
(Ta = -40 to +85C, VDD = 8 to 18V) Parameter D/A Output Voltage Error Reference Voltage Accuracy Condition -- Note 1 Min. -- -- Typ. -- -- Max. 3 6 Unit % %
Note:
1. Reference voltage is 6.6V typical.
Keyscan Characteristics
(Ta = -40 to +85C, VDD = 8 to 18V) Parameter Keyscan Cycle Time Keyscan Pulse Width Condition fOSC=3.3 MHz fOSC=3.3 MHz Min. 275 55 Typ. 390 78 Max. 640 128 Unit ms ms
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FEDL1200V-03 Semiconductor MSC1200-01/1200V-01
TIMING DIAGRAM
tCSW tCSL
3.8V CS 0.8V tCSS tCW CLOCK 3.8V 0.8V tDS tDH 3.8V DATA I/O (INPUT) 0.8V VALID VALID tDS fC tCW
tCSH
tDH
Figure 1 Data Input Timing
CS
3.8V 0.8V tCSS tCSH
CLOCK
3.8V 0.8V tPD tPD
DATA I/O 3.8V (OUTPUT) DATA OUT 0.8V
Figure 2 Data Output Timing
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FEDL1200V-03 Semiconductor MSC1200-01/1200V-01
TIMING DIAGRAM (Continued)
8V VDD 0V tPCS tPOF tPRZ
CS
3.8V
Figure 3 Power-On Timing
tCSW
CS
3.8V
tODS tR 80% 20%
tODS tR
SEG1-30 GRID1, 2
Figure 4 SEG & GRID Output Timing
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FEDL1200V-03 Semiconductor MSC1200-01/1200V-01
FUNCTIONAL DESCRIPTION
Power-on Reset The IC is initialized by the built-in power-on reset circuit at power-on. The status of the internal circuit after initialization is as follows; 1) Shift registers and latches are reset. 2) Analog dimming is selected. 3) Digital dimming data register is reset. 4) Display data input mode is selected. Data Input Data input is valid only when the high level is applied to the "CS" pin. Input data is input into the shift register through "DATA I/O" pin at the rising edge of CLOCK. The data is automatically loaded to latches at the falling edge of "CS" signal. [Data Format] 1) Display Data Input Mode Input data : 64 bits VF display data : 60 bits Mode select data : 4 bits
First In Bit 64 63 62 D57 Display Data (12 bits) ... 53 D48 52 M3 51 M2 50 M1 49 M0 48 D47 ... 3 D2 Display Data (48 bits) 2 D1 1 D0
D59 D58
Mode Data (4 bits)
2) Correspondence between segment outputs and shift register bits
30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 SEGn 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 GRID1 Bit 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 GRID2
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FEDL1200V-03 Semiconductor 3) Digital Dimming Data Input Mode Input data : 16 bits Digital dimming data : 11 bits Mode select data : 4 bits
Bit 64 xx 63 11 MSB Dimming Data 62 10 61 9 60 8 59 7 58 6 57 5 56 4 55 3 54 2 53 1 LSB Mode Data 52 M 3 51 M 2 50 M 1 49 First In M 0
MSC1200-01/1200V-01
(MSB) X X X X 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
INPUT DATA 0 0 1 1 0 0 1 1 0 0 1 1 0 0 0 1 0 0 0 1 0 0 0 1
(LSB) 0 1 0 1
DUTY CYCLE 0/2048 1/2048 2032/2048 2032/2048
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FEDL1200V-03 Semiconductor 4) Function Mode
Mode S1 S2 S3 S4 S5 S6 S7 S8 S9 SA M3 0 0 0 0 0 0 0 0 1 1 M2 0 0 1 0 1 1 0 1 0 0 M1 0 1 0 0 1 1 1 0 0 0 M0 0 1 1 1 1 0 0 0 0 1 Display Data Input Analog Dimming Select Digital Dimming Select Digital Dimming Data Input & Digital Dimming Select Keyscan Data Output Display Data Input & Keyscan Data Output Display Data Input & Analog Dimming Select Display Data Input & Digital Dimming Select Keyscan Data Output & Keyscan Stop Keyscan STOP Function
MSC1200-01/1200V-01
Note: Other combinations are used for test modes.
5) Analog Dimming Mode Analog dimming is automatically selected when the VPARK pin is set to the high level after power-on. Therefore, when digital dimming is used, mode setting is required before the VPARK pin is set to the high level. The output duty ratio for analog dimming is 12.5% maximum. The correspondence between threshold voltage and output duty ratio is shown in VDIN Threshold Dimming Voltage VS. PWM Duty Cycle.
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FEDL1200V-03 Semiconductor Keyscan Keyscanning is started only when depression or release of any key is detected in order to minimize noise caused by scanning signal. Then, keyscanning is continued until the keyscan stop mode signal is sent from a microcomputer. The INT pin goes to the high level at the completion of 1-cycle scanning after the keyscan start, so the (high level) signal sent from the INT pin can be used as an interrupt signal. [Keyscan Timing] MSC1200-01/1200V-01
ROW 0
ROW 1 ROW 2
ROW 3
ROW 4 1 Cycle INT
Depress/Release
Keyscan stop mode is selected.
Note: Keyscanning cannot be stopped by selecting the keyscan stop mode only once if: - keyscanning is started after depression or release of any key is detected, and then - a key is depressed or released again before the keyscan stop mode is selected. To stop keyscanning, it is required to select the keyscan stop mode once again.
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FEDL1200V-03 Semiconductor [Example] A) When Key Input Status is Changed
Depress Release
MSC1200-01/1200V-01
INT
Keyscan
Keyscan stop
Keyscan
Keyscan stop
CS Keyscan stop
SA
S5 Keyscan data output Keyscan stop
SA
S5 Keyscan data output
B) When Key Input Status is Changed before Keyscan Stop Mode Select
Depress
Release
*1 Keyscan Keyscan Keyscan Stop
INT
CS
Keyscan stop
SA
S5 Keyscan data output Keyscan stop
SA
S5 Keyscan data output
*1: Keyscanning resumes after short period of keyscan stop.
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FEDL1200V-03 Semiconductor Keyscan Data Output When keyscan data output mode is selected, "DATA I/O" pin is changed to an output mode. Then, 30 bits of keyscan data come out from "DATA I/O" pin synchronizing with the rising edge of the clock. After the completion of 30 bits data output, the IC returns to the display data input mode synchronizing with the falling edge of CS. [Data Format] 1) Keyscan Data Stop Mode Since the DATA I/O pin goes to the output mode after the keyscan stop mode signal is received, be sure to output the keyscan data. Input data : 16 bits Mode select data : 4 bits
Bit 64 xx 63 xx 62 xx 61 xx 60 xx 59 xx 58 xx 57 xx 56 xx 55 xx 54 xx 53 xx 52 M 3 51 M 2 50 M 1 49 First In M 0
MSC1200-01/1200V-01
Mode Data
2) Keyscan Data Output Mode Input data : 30 bits Output data : 30 bits
CLOCK 30 S 45 29 S 44 28 S 43 ..... ..... 9 S 12 8 S 11 7 S 10 6 S 05 5 S 04 4 S 03 3 S 02 2 S 01 1 First Out S Keyscan Data 00
Sxx
ROW COLUMN 3) Key switch matrix for COLUMN input and ROW output
ROW0 S00 S01 S02 S03 S04 S05 = ROW1 S10 S11 S12 S13 S14 S15 ROW2 S20 S21 S22 S23 S24 S25 ROW3 S30 S31 S32 S33 S34 S35 ROW4 S40 S41 S42 S43 S44 S45 COLUMN0 COLUMN1 COLUMN2 COLUMN3 COLUMN4 COLUMN5
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FEDL1200V-03 Semiconductor MSC1200-01/1200V-01
GRID/SEG Driver Operation and Digital/Analog Dimming Operation Figure 5 shows the output timing of the GRID and SEG driver when the VPARK is the "H" level. Figure 6 shows the output timing of the GRID and SEG drivers for the digital diming mode operation. Figure 7 shows the output timing of the GRID and SEG drivers for the analog dimming mode operation.
1 Frame 4096 bit times GRID1 16 bit times GRID2 2032 bit times 6 bit times
SEG1-30 2038 bit times 10 bit times
Figure 5 GRID and SEG Output Timing (VPARK="H") Note: 1 bit time = TOSC (4/fOSC) = 1.2ms (typ.)
1 Frame 4096 bit times
GRID1
16 bit times GRID2 2032 bit times 6 bit times
SEG1-30 2038 bit times 10 bit times
Figure 6 GRID and SEG Output Timing (Digital Dimming Mode) Notes: 1. Shown above is the timing in the digital dimming mode with the duty cycle of 2032/ 2048 at VPARK = "L". 2. The length of time that the grids and the segments are turned on is specified with respect to 11 bits of the ditigal dimming data. 3. 1 bit time = TOSC (4/fOSC) = 1.2ms (typ.) 19/26
FEDL1200V-03 Semiconductor MSC1200-01/1200V-01
1 Frame 4096 bit times GRID1
2048 bit times GRID2 Max. 256 bit times
SEG1-30
Figure 7 GRID and SEG Output Timing (Analog Dimming Mode) Notes: 1. Shown above is the timing for the GRID and SEG Drivers in the analog dimming mode at VPARK = "L". 2. 1 bit time = TOSC (4/fOSC) = 1.2ms (typ.)
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FEDL1200V-03 Semiconductor PLA Code Table MSC1200-01/1200V-01
SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60
PIN PIN PIN PIN PIN PIN PIN PIN PIN PIN PIN PIN PIN PIN PIN PIN PIN PIN PIN PIN PIN PIN PIN PIN PIN PIN PIN PIN PIN PIN
24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53
PIN NAME SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10
BIT 1, BIT 2, BIT 3, BIT 4, BIT 5, BIT 6, BIT 7, BIT 8, BIT 9, BIT10, BIT11, BIT12, BIT13, BIT14, BIT15, BIT16, BIT17, BIT18, BIT19, BIT20, BIT21, BIT22, BIT23, BIT24, BIT25, BIT26, BIT27, BIT28, BIT29, BIT30,
OUTPUT BIT 1, 31 BIT 2, 32 BIT 3, 33 BIT 4, 34 BIT 5, 35 BIT 6, 36 BIT 7, 37 BIT 8, 38 BIT 9, 39 BIT 10, 40 PIN NAME SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 OUTPUT BIT 11, 41 BIT 12, 42 BIT 13, 43 BIT 14, 44 BIT 15, 45 BIT 16, 46 BIT 17, 47 BIT 18, 48 BIT 19, 49 BIT 20, 50 PIN NAME SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 OUTPUT BIT 21, 51 BIT 22, 52 BIT 23, 53 BIT 24, 54 BIT 25, 55 BIT 26, 56 BIT 27, 57 BIT 28, 58 BIT 29, 59 BIT 30, 60
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FEDL1200V-03 Semiconductor VDIM Threshold Dimming Voltage VS. PWM Duty Cycle
PWM Duty Cycle Pulse Count 256/2048 240/2048 224/2048 208/2048 192/2048 184/2048 176/2048 168/2048 160/2048 152/2048 144/2048 136/2048 128/2048 120/2048 112/2048 104/2048 96/2048 92/2048 88/2048 84/2048 80/2048 76/2048 72/2048 68/2048 64/2048 60/2048 % 12.5 11.7 10.9 10.2 9.38 8.98 8.59 8.20 7.81 7.42 7.03 6.64 6.25 5.86 5.47 5.08 4.69 4.49 4.30 4.10 3.91 3.71 3.52 3.32 3.13 2.93 Threshold Pulse Step PWM Duty Cycle Voltage Number Pulse Count % Vref 26 56/2048 2.73 4.200 25 52/2048 2.54 4.130 24 48/2048 2.34 4.070 23 46/2048 2.25 4.000 22 44/2048 2.15 3.930 21 42/2048 2.05 3.890 20 40/2048 1.95 3.850 19 38/2048 1.86 3.810 18 36/2048 1.76 3.770 17 1.66 34/2048 3.725 16 1.56 32/2048 3.680 15 1.46 30/2048 3.625 14 28/2048 1.37 3.580 26/2048 13 1.27 3.525 12 24/2048 1.17 3.460 11 23/2048 1.12 3.400 10 22/2048 1.07 3.340 9 21/2048 1.03 3.305 8 20/2048 0.98 3.270 7 19/2048 0.93 3.240 6 18/2048 0.88 3.200 5 17/2048 0.83 3.160 4 16/2048 0.78 3.120 3 15/2048 0.73 3.080 2 14/2048 0.68 3.040 1 13/2048 0.63 2.93 0 VDD=12.8V Threshold Voltage 3.000 2.950 2.900 2.850 2.820 2.800 2.770 2.740 2.710 2.680 2.650 2.615 2.580 2.540 2.500 2.470 2.450 2.430 2.410 2.390 2.370 2.340 2.320 2.295 2.270 2.245 0.000
MSC1200-01/1200V-01
Pulse Step Number 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27
Note: A threshold voltage more than 5V cannot be set.
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FEDL1200V-03 Semiconductor MSC1200-01/1200V-01
APPLICATION CIRCUITS
(A) Digital Dimming
1/2-Duty VF Display Tube
Driver SEG1 SEG30 G1 G2 COLUMN5 COLUMN4 COLUMN3 COLUMN2 COLUMN1 COLUMN0 MSC1200-01 ROW0 ROW1 ROW2 ROW3 2R VPARK VDIM R ROW4 Keyboard
Microcomputer
VDD GND INT CS DATAI/O CLOCK OSC1
Luminance Control Small Parking Resistor Lamp SW
OSC0
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FEDL1200V-03 Semiconductor MSC1200-01/1200V-01
(B) Analog Dimming
1/2-Duty VF Display Tube
Driver SEG1 SEG30 G1 G2 COLUMN5 COLUMN4 COLUMN3 COLUMN2 COLUMN1 COLUMN0 MSC1200-01 ROW0 ROW1 ROW2 ROW3 2R VPARK R VDIM 2R Dashboard Lamp R The setting voltage must not exceed 5V. ROW4 Keyboard
Microcomputer
VDD GND INT CS DATAI/O CLOCK OSC1
Small Parking Lamp SW
OSC0
Luminance Control Resistor
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FEDL1200V-03 Semiconductor MSC1200-01/1200V-01
PACKAGE DIMENSIONS
(Unit : mm)
QFP56-P-910-0.65-2K
Mirror finish
Oki Electric Industry Co., Ltd.
Package material Lead frame material Pin treatment Package weight (g) Rev. No./Last Revised
Epoxy resin 42 alloy Solder plating (5 mm) 0.43 TYP. 4/Vov. 28, 1996
Notes for Mounting the Surface Mount Type Package The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki's responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times).
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FEDL1200V-03 Semiconductor MSC1200-01/1200V-01
NOTICE
1. The information contained herein can change without notice owing to product and/or technical improvements. Before using the product, please make sure that the information being referred to is up-to-date. The outline of action and examples for application circuits described herein have been chosen as an explanation for the standard action and performance of the product. When planning to use the product, please ensure that the external conditions are reflected in the actual circuit, assembly, and program designs. When designing your product, please use our product below the specified maximum ratings and within the specified operating ranges including, but not limited to, operating voltage, power dissipation, and operating temperature. Oki assumes no responsibility or liability whatsoever for any failure or unusual or unexpected operation resulting from misuse, neglect, improper installation, repair, alteration or accident, improper handling, or unusual physical or electrical stress including, but not limited to, exposure to parameters beyond the specified maximum ratings or operation outside the specified operating range. Neither indemnity against nor license of a third party's industrial and intellectual property right, etc. is granted by us in connection with the use of the product and/or the information and drawings contained herein. No responsibility is assumed by us for any infringement of a third party's right which may result from the use thereof. The products listed in this document are intended for use in general electronics equipment for commercial applications (e.g., office automation, communication equipment, measurement equipment, consumer electronics, etc.). These products are not authorized for use in any system or application that requires special or enhanced quality and reliability characteristics nor in any system or application where the failure of such system or application may result in the loss or damage of property, or death or injury to humans. Such applications include, but are not limited to, traffic and automotive equipment, safety devices, aerospace equipment, nuclear power control, medical equipment, and life-support systems. Certain products in this document may need government approval before they can be exported to particular countries. The purchaser assumes the responsibility of determining the legality of export of these products and will take appropriate and necessary steps at their own expense for these. No part of the contents contained herein may be reprinted or reproduced without our prior permission. MS-DOS is a registered trademark of Microsoft Corporation.
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Copyright 2000 Oki Electric Industry Co., Ltd.
Printed in Japan
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